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DOI:10.1109/EPTC47984.2019.9026578 - Corpus ID: 212648221
@article{Ji2019ModellingAC, title={Modelling and characterization on wafer to wafer hybrid bonding technology for 3D IC packaging}, author={Lin Ji and Fa Xing Che and Hongmiao Ji and H.Y. Li and Masaya Kawano}, journal={2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)}, year={2019}, pages={87-94}, url={https://api.semanticscholar.org/CorpusID:212648221}}- L. Ji, F. Che, M. Kawano
- Published in Electronic Packaging… 1 December 2019
- Engineering, Materials Science
For Wafer to Wafer Hybrid Bonding (W2W-HB) technology, warpage mitigation and precise Cu to Cu bonding are required to ensure a robust bonding integrity. This paper documents a numerical methodology using the Finite Element Analysis (FEA) tool to investigate the impact of various design and process parameters on two-layer wafer to wafer bonding. The risk of poor bonding integrity associated with inappropriate design and process parameters selected are discussed. The attempt of this paper is to…
17 Citations
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17 Citations
- L. JiF. CheH. JiHong Yu LiM. Kawano
- 2020
Engineering, Materials Science
2020 IEEE 70th Electronic Components and…
This paper presents a 3D advanced numerical modelling methodology to simulate the bonding process for fine pitch TSV wafers using wafer to wafer hybrid bonding (W2W-HB) technology from…
- 19
- L. JiF. CheH. JiHong Yu LiM. Kawano
- 2020
Engineering, Materials Science
IEEE Transactions on Components, Packaging and…
This article focuses on the 3-D modeling methodology development of the wafer-to-wafer hybrid bonding (W2W-HB) annealing process, and the resulting debonding risk for both Cu and dielectric bonding is assessed by comparing the peak interfacial peeling stresses for various scenarios.
- 25
- H. JiL. JiF. CheHong-Yu LiK. ChuiM. Kawano
- 2020
Engineering, Materials Science
2020 IEEE International Symposium on the Physical…
This article investigates the W2W alignment accuracy of hybrid bonding process, and studies the defects in the unbonded zone around the Cu pad bonding area.
- 9
- H. LiM. KawanoL. JiH. JiC. S. Lim
- 2020
Engineering, Materials Science
2020 IEEE 22nd Electronics Packaging Technology…
This paper describes the demonstration of a 4-layer wafer stack using a combination of face-to-face and back-to-back, wafer-to-wafer hybrid bonding process. Details of process flow, process…
- 4
- L. JiT. ChaiSharon Pei Siang Lim
- 2022
Engineering, Materials Science
2022 IEEE 24th Electronics Packaging Technology…
This paper presents a numerical study using Finite Element Analysis modelling approach to predict the wafer warpage during a 3D chiplet package fabrication process. To mitigate the wafer warpage,…
- 2
- Sasi Kumar TippabhotlaL. JiC. Choong
- 2022
Engineering, Materials Science
2022 IEEE 24th Electronics Packaging Technology…
Development of chip to wafer hybrid bonding (C2W-HB) process is essential to achieve direct bonding of fine pitch (≤ 10 μm) Cu interconnects for heterogeneous integration. As the polymer mechanical…
- 2
- Haozhong WangHongtao ChenJunshan XiangXiaofeng Yang
- 2023
Engineering, Materials Science
2023 24th International Conference on Electronic…
Cu/SiO2 hybrid bonding technology is proposed as a solution for the increasing demand of 3D packaging for higher I/O density and higher bandwidth applications. In this paper, a numerical approach to…
- Guoqiang ZhaoYanping ZengYi Zhao
- 2024
Engineering, Materials Science
2024 IEEE 10th Electronics System-Integration…
In this work, the influence of the most important parameters on stress around hybrid bonding units is explored by 3D finite element modeling approach. The impact of pad shape, size, pitch, density,…
- Ge LiQiushi KangF. NiuChenxi Wang
- 2022
Engineering, Materials Science
Microelectronics International
PurposeBumpless Cu/SiO2 hybrid bonding, which this paper aims to, is a key technology of three-dimensional (3D) high-density integration to promote the integrated circuits industry’s continuous…
- 6
- Sasi Kumar TippabhotlaL. JiC. Choong
- 2023
Engineering, Materials Science
2023 IEEE 25th Electronics Packaging Technology…
Advanced computing applications such as internet-of-things, autonomous driving and artificial intelligence require integrated chips with fine pitch interconnections. Heterogeneous integration (HI) of…
- 1
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4 References
- F. CheH. LiXiaowu ZhangShan GaoK. Teo
- 2012
Engineering, Materials Science
IEEE Transactions on Components, Packaging and…
Through-silicon via (TSV) technology has been widely investigated recently for 3-D electronic packaging integration. Reducing TSV wafer warpage is one of the most challenging concerns for…
- 49
- F. CheW. N. PutraA. HeryantoA. TriggXiaowu ZhangC. Gan
- 2013
Engineering, Materials Science
IEEE Transactions on Components, Packaging and…
The through-silicon via (TSV) approach is essential for 3-D integrated circuit (3-DIC) packaging technology. TSV fabrication process, however, is still facing several challenges. One of the widely…
- 74
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